Xwire: Master configuration
In the Xwire master you need a table in NVEM0 that defines all the data connections that are to take place. The tables in master and slave(s) must be consistent with each other, or it won't work.
In the master the table contains one 5-byte entry per slave. The entry defines the slave address, and the address and block lengths within the Master of the Tx and Rx RAM blocks for the slave. The general format is as follows:
NVEM0 XWireTab: NV0Byte SlaveAddr0,TxRAMStart0,TxRAMLen0,RxRAMStart0,RxRAMLen0 NV0Byte SlaveAddr1,TxRAMStart1,TxRAMLen1,RxRAMStart1,RxRAMLen1 NV0Byte SlaveAddr2,TxRAMStart2,TxRAMLen2,RxRAMStart2,RxRAMLen2 ... etc NV0Byte 255 ;End of table sentinel.
SlaveAddr0, SlaveAddr1
etc are the Xwire addresses of the slave 0, slave 1 etc. Legal values are 0 to 253.
TxRAMStart0, TxRAMStart1
etc are the addresses in Master RAM where data is to be taken from and sent to the slaves.
TxRAMLen0, TxRAMLen1
etc are the number of bytes that are to be sent to the respective slaves.
RxRAMStart0, RxRAMStart1
etc are the addresses in master RAM where data received from the respective slaves is to be stored.
RxRAMLen0, RxRAMLen1
etc are the number of bytes to expect (and store in RAM) from the respective slaves.
The final 255 is vital. It signals the end of the table.
Notice that the master does not know where in the slave the data is located.
Example:
Suppose we have two slaves. The first slave is to receive 2 bytes of data from the master and send back 3 bytes of data. The slaves are set to Xwire bus addresses 8 and 76. We decide that data to the first slave will be taken from local (master) RAM address 19 and 20, and data from the first slave will be stored in RAM at 21 through 23. Our table might look like this:
NVEM0 XWireTab: NV0Byte 8,19,2,21,3 ;First slave NV0Byte 76,57,5,85,2 ;Second slave NV0Byte 255 ;End of table
Can you work out where the data to and from the second slave are located? How many bytes are transferred in each direction? (Answer at the bottom of the page).
Normally you should use symbolic names, so it might look more like this:
S0TxRAM: mEQU 19,2 ;Define Xwire Tx RAM for slave 0 S0RxRAM: mEQU 21,3 ;Define Xwire Rx RAM for slave 0 S0Address: EQU 8 ;Xwire address of slave 0 S1TxRAM: mEQU 57,5 ;Define Xwire Tx RAM for slave 1 S1RxRAM: mEQU 85,2 ;Define Xwire Rx RAM for slave 1 S1Address: EQU 76 ;Xwire address of slave 1 NVEM0 XWireTab: NV0Byte S0Address,S0TxRAM,2,S0RxRAM,3 NV0Byte S1Address,S1TxRAM,5,S1RxRAM,2 NV0Byte 255
The configuration will be invoked by the following instruction placed in the early initialization code for the master
XwireMaster
XWireTab
-----------------------------------------------
Answer to question: We send the second slave 5 bytes starting at 57. We expect back 2 bytes which will be stored at 85 and 86.